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general description the MAX3746 multirate limiting amplifier functions as a data quantizer for sonet, fibre-channel, and gigabit ethernet optical receivers. the amplifier accepts a wide range of input voltages and provides selectable-level, current-mode logic (cml) output voltages with con- trolled edge speeds. a received-signal-strength indica- tor (rssi) is available when the MAX3746 is dc-coupled to the max3744/max3724 sfp transim- pedance amplifier (tia). a receiver consisting of the max3744/max3724 and the MAX3746 can provide up to 19db rssi dynamic range. additional features include a programmable loss-of-signal (los) detect, an optional disable function (disable), and an output-signal polarity reversal (outpol). output dis- able can be used to implement squelch. the combination of the MAX3746 and the max3744/ max3724 allows for the implementation of all the small- form-factor sff-8472 digital diagnostic specifications using a standard 4-pin to-46 header. the MAX3746 is pin-for-pin compatible with the max3748a limiting amplifier and consumes 30% less power. the MAX3746 is packaged in a 3mm x 3mm, 16-pin qfn package. applications gigabit ethernet sff/sfp transceiver modules fibre-channel sff/sfp transceiver modules multirate oc-12 to oc48-fec sff/sfp transceiver modules features ? sfp reference design available ? low 115mw power consumption ? 16-pin qfn package with 3mm x 3mm footprint ? 70ps rise and fall time ? loss-of-signal with programmable threshold ? rssi interface (with max3744/max3724 tia) ? output disable ? polarity select ? 8.4ps p-p deterministic jitter (3.2gbps) ? improved emi performance ? selectable cml output levels ? pin compatible with max3748a MAX3746 low-power, 622mbps to 3.2gbps limiting amplifier ________________________________________________________________ maxim integrated products 1 ordering information 19-3386; rev 0; 8/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package pkg code MAX3746ete -40? to +85? 16 qfn t1633f-3 typical operating circuits continued at end of data sheet. pin configuration appears at end of data sheet. MAX3746 max3744 tia ds1859 3-input diagnostic monitor r1 3k ? c1 0.1 f in+ in- rssi th disable los outpol v cc gnd 4.7k ? to 10k ? los 2.97v to 3.6v out+ 50 ? 0.1 f out- 50 ? 0.1 f serdes r th = 14k ? supply filter host filter v cc _rx 4-pin to header host board sfp optical receiver t ypical operating circuits
MAX3746 low-power, 622mbps to 3.2gbps limiting amplifier 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. power-supply voltage (v cc ) .................................-0.5v to +4.5v voltage at in+, in- ..........................(v cc - 2.4v) to (v cc + 0.5v) voltage at disable, outpol, rssi, los, th ...................................................-0.5v to (v cc + 0.5v) current into los.....................................................1ma to +9ma differential input voltage (in+ - in-) .....................................2.5v continuous current at cml outputs (out+, out-) ................................................-25ma to +25ma continuous power dissipation (t a = + 70?) 16-pin qfn (derate 17.7mw above +70?) .....................1.4w operating junction temperature range (t j ) ....-55? to +150? storage ambient temperature range (ts) .......-55? to +150? electrical characteristics (v cc = +2.97v to +3.63v, cml output load is 50 ? to v cc , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?, unless otherwise specified. the data input transition time is controlled by 4th-order bessel filter with f -3db = 0.75 x 2.667ghz for all data rates of 2.667gbps and below, and with f -3db = 0.75 x 3.2ghz for a data rate of 3.2gbps.) parameter symbol conditions min typ max units single-ended input resistance r in single ended to v cc 42 50 58 ? se s 11 s i ng l e end ed , f < 3gh z, d u t i s p ow er ed on 14 input return loss diff s 11 differential, f < 3ghz, dut is powered on 15 db input sensitivity v in-min (note 1) 2 4 mv p-p input overload v in-max (note 1) 1200 mv p-p single-ended output resistance r out single ended to v cc 42 50 58 ? output return loss diff s 22 differential, f < 3ghz, dut is powered on 20 db 4mv p-p < v in < 1200mv p-p , outpol connected to v cc or gnd 600 800 1000 cml differential output voltage 4mv p-p < v in < 1200mv p-p , outpol open or connected to 30k ? 400 500 600 mv p-p differential output signal when disabled outputs ac-coupled, v in-max applied to input (note 2) 10 mv p-p k28.5 pattern at 3.2gbps (note 2) 8.4 18 k28.5 pattern at 3.2gbps at t a = +100 c 10.2 2 23 - 1 prbs equivalent at 2.7gbps (note 2) 11.6 23 2 23 - 1 prbs equivalent pattern at 2.7gbps at t a = +100 c 13.1 k28.5 pattern at 2.1gbps 8 20 k28.5 pattern at 2.1gbps at t a = +100 c 9.7 2 23 - 1 prbs equivalent pattern at 622mbps (note 2) 42.5 69 deterministic jitter (note 3) dj 2 23 - 1 prbs equivalent pattern at 622mbps at t a = +100 c 47.8 ps p-p
MAX3746 low-power, 622mbps to 3.2gbps limiting amplifier _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +2.97v to +3.63v, cml output load is 50 ? to v cc , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = 3.3v, t a = +25?, unless otherwise specified. the data input transition time is controlled by 4th-order bessel filter with f -3db = 0.75 x 2.667ghz for all data rates of 2.667gbps and below, and with f -3db = 0.75 x 3.2ghz for a data rate of 3.2gbps.) parameter symbol conditions min typ max units random jitter input = 4mv p-p (notes 2, 4) 3 7 ps rms data output transition time 4mv p-p < v inp-p < 1200mv p-p , 20% to 80% (note 2) 70 114 ps input-referrednoise (note 2) 150 ? rms low-frequency cutoff 20 khz includes the cml output current; outpol connected to v cc or gnd 35 41.5 includes the cml output current; outpol open or connected to 30k ? to gnd 29 35 power-supply current i cc excludes the cml output current and the cm_rssi circuitry; outpol connected to v cc or gnd (note 5) 20 25 ma power-supply noise rejection psnr f < 2mhz 40 db loss-of-signal (notes 2, 6) los hysteresis 10 log (v deassert / v assert ) 1.25 2.2 db los assert/deassert time (note 7) 2.3 50 ? low los assert level r th = 2k ? 2.6 4 6.4 mv p-p low los deassert level r th = 2k ? 6 9.6 mv p-p medium los assert level r th = 14k ? ? 42 54.7 mv p-p high los assert level r th = 25k ? 36 50 54.3 mv p-p high los deassert level r th = 25k ? 84 114 mv p-p cm_rssi specification rssi current gain a rssi i rssi / i cm_rssi (note 8) 0.031 v cm to i rssi 3db bandwidth 40 khz input-referred rssi current stability i rss i a rss i input < 6.6ma, 0v v rssi 2.5v (note 9) -40 +36 ? rssi output compliance voltage v rssi 0 2.0 v ttl/cmos i/o los output high voltage v oh r los = 4.7k ? to 10k ? to vcc_host (3v) 2.4 v los output low voltage v ol r los = 4.7k ? to 10k ? to vcc_host (3.6v) 0.4 v
t ypical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) MAX3746 low-power, 622mbps to 3.2gbps limiting amplifier 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = +2.97v to +3.63v, cml output load is 50 ? to v cc , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?, unless otherwise specified. the data input transition time is controlled by 4th-order bessel filter with f -3db = 0.75 x 2.667ghz for all data rates of 2.667gbps and below, and with f -3db = 0.75 x 3.2ghz for a data rate of 3.2gbps.) parameter symbol conditions min typ max units disable input high v ih 2.0 v disable input low v il 0.8 v disable input current r los = 4.7k ? to 10k ? to vcc_host 10 ? note 1: between sensitivity and overload, all ac specifications are met. note 2: guaranteed by design and characterization. note 3: the deterministic jitter caused by the filter is not included in the dj generation specification. note 4: random jitter was measured without using a filter at the input. note 5: the supply current measurement excludes the cml output currents by connecting the cml outputs to a separate v cc . (see figure 1.) note 6: hysteresis is calculated as 10 log (v deassert / v assert ). unless otherwise specified, the data rate for all los detect speci- fications varies from 622mbps up to 3.2gbps, and the patterns are 1010 or 2 23 - 1 prbs. note 7: the signal is switched between two amplitudes, signal_on and signal _off as shown in figure 2. note 8: i cm_rssi is the input common-mode current. i rssi is the current at the rssi output. note 9: stability is defined as the variation over temperature and power supply with respect to the typical gain of the part. supply current vs. temperature MAX3746 toc01 temperature ( c) current (ma) 90 80 60 70 -10 0 10 20 30 40 50 -30 -20 10 20 30 40 50 60 70 80 90 100 0 -40 100 cml outputs included cml outputs not included outpol = v cc transfer function MAX3746 toc02 differential input (mv p-p ) differential output (mv p-p ) 5 4 3 2 1 100 200 300 400 500 600 700 800 900 0 06 outpol = v cc random jitter vs. temperature (input level 10mv p-p ) MAX3746 toc03 temperature ( c) random jitter (ps rms ) 90 80 60 70 -10 0 10 20 30 40 50 -30 -20 1 2 3 4 5 6 7 8 9 10 0 -40 100
MAX3746 low-power, 622mbps to 3.2gbps limiting amplifier _______________________________________________________________________________________ 5 random jitter vs. input amplitude MAX3746 toc04 differential input (mv p-p ) random jitter (ps rms ) 35 30 20 25 10 15 5 1 2 3 4 5 6 7 8 9 10 0 040 bit-error ratio vs. input voltage MAX3746 toc05 input voltage (mv p-p ) bit-error ratio (10 -12 ) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 200 400 600 800 1000 1200 0 0 5.0 deterministic jitter vs. input common-mode voltage (2.7gbps, k28.5) MAX3746 toc06 common-mode voltage (v cc + x) deterministic jitter (ps p-p ) -0.1 -0.2 -0.9 -0.8 -0.7 -0.5 -0.4 -0.6 -0.3 12 14 16 18 20 22 24 10 -1.0 0 output eye diagram (minimum input) MAX3746 toc07 50ps/div 100mv/div 3.2gbps, k28.5, 4mv p-p output eye diagram (maximum input) MAX3746 toc08 50ps/div 100mv/div 3.2gbps, k28.5, 1200mv p-p output eye diagram (minimum input) MAX3746 toc09 100ps/div 100mv/div 2.7gbps, 2 23 - 1 prbs, 4mv p-p output eye diagram (maximum input) MAX3746 toc10 50ps/div 100mv/div 2.7gbps, 2 23 - 1 prbs, 1200mv p-p output eye diagram at +100 c (minimum input) MAX3746 toc11 50ps/div 100mv/div 2.7gbps, 2 23 - 1 prbs, 4mv p-p assert/deassert levels vs. r th max3726 toc12 r th (k ? ) los assert/deassert (mv p-p ) 20 10 20 40 60 80 100 120 0 030 deassert assert t ypical operating characteristics (continued) (v cc = +3.3v, t a = +25?, unless otherwise noted.)
MAX3746 low-power, 622mbps to 3.2gbps limiting amplifier 6 _______________________________________________________________________________________ input return gain (sdd11) (input signal level = -50dbm) (output disabled) MAX3746 toc13 frequency (hz) gain (db) 1g -30 -20 -10 0 10 20 30 -40 100m 10g output return gain (sdd22) (input signal level = -50dbm) (with input dc offset) MAX3746 toc14 frequency (mhz) gain (db) 1g -30 -20 -10 0 10 20 30 -40 100m 10g deterministic jitter vs. input offset voltage (2.667gbps, k28.5) MAX3746 toc15 input offset voltage (mv p-p ) deterministic jitter (ps p-p ) 5 4 2 3 -4 -3 -2 -1 0 1 -5 2 4 6 8 10 12 14 16 18 20 0 -6 6 los hysteresis vs. temperature (2.667gbps, 2 23 - 1 prbs) MAX3746 toc16 temperature ( c) 10 log (deassert/assert) (db) 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 1 2 3 4 5 6 0 -40 r th = 25k ? r th = 14k ? r th = 2.00k ? rssi current vs. input tia current (max3744 and MAX3746) MAX3746 toc17 input tia current ( a) output rssi current ( a) 900 800 700 600 500 400 300 200 100 100 200 300 400 500 600 700 0 0 1000 rssi current vs. optical power (max3744 and MAX3746) MAX3746 toc19 optical power (dbm) output rssi current ( a) -5 -10 -15 -20 -25 100 200 300 400 500 600 700 0 -30 0 single-ended output signal MAX3746 toc18 200ps/div 50mv/div 2.7gbps, 2 7 - 1, 1000mv p-p t ypical operating characteristics (continued) (v cc = +3.3v, t a = +25?, unless otherwise noted.)
MAX3746 low-power, 622mbps to 3.2gbps limiting amplifier _______________________________________________________________________________________ 7 pin name function 1, 4 v cc1 supply voltage 2 in+ noninverted input signal, cml 3 in- inverted input signal, cml 5th loss-of-signal threshold pin. resistor to ground (r th ) sets the los threshold. connecting this pin to v cc disables the los circuitry and reduces power consumption. 6 disable disable input, cmos/ttl. the data outputs are held static when this pin is asserted high. the los function remains active when the outputs are disabled. 7 los noninverted loss-of-signal output. los is asserted high when the signal drops below the assert threshold set by the th input. the output is open collector. 8, 16 gnd supply ground 9 outpol output polarity control. connect to gnd for an inversion of polarity through the limiting amplifier and connect to v cc for normal operation. see table 1 for all settings. 10 out- inverted data output, cml 11 out+ noninverted data output, cml 12 v cc2 output supply 13 rssi received-signal-strength indicator. this current output can be used to obtain a ground-referenced voltage proportional to the photodiode current with the max3744 by connecting an external resistor between this pin and gnd. 14,15 n.c. no connection. leave open. ep exposed pad connect the exposed pad to board ground for optimal electrical and thermal performance. pin description detailed description the MAX3746 limiting amplifier consists of an input buffer, a multistage amplifier, offset-correction circuitry, an output buffer, power-detection circuitry, and signal- detect circuitry (see the functional diagram ). input buffer the input buffer is shown in figure 3. it provides 50 ? ter- mination for each input signal in+ and in-. the MAX3746 can be dc- or ac-coupled to a tia (tia output offset degrades receiver performance if dc-coupled). the cml input buffer is optimized for the max3744/ max3724 tia. gain stage the high-bandwidth multistage amplifier provides approximately 60db of gain. offset correction loop the MAX3746 is susceptible to dc offsets in the signal path because it has high gain. in communication sys- tems using nrz data with a 50% duty cycle, pulse- width distortion present in the signal, or generated in the transimpedance amplifier, appears as an input off- set and is reduced by the offset correction loop. cml output buffer the MAX3746 limiting amplifier? cml output provides high tolerance to impedance mismatches and inductive connectors. the outpol setting programs the output current. connecting the disable pin to v cc disables the output. if the los pin is connected to the disable pin, the outputs out+ and out- are at a static voltage (squelch) whenever the input signal level drops below the los threshold. the output common mode remains constant when the part is disabled. the output buffer can be ac- or dc-coupled to the load (figure 4).
MAX3746 power detect and loss-of-signal indicator the MAX3746 is equipped with multirate los circuitry that indicates when the input signal is below a pro- grammable threshold, set by resistor r th at the th pin (see the typical operating characteristics for appropri- ate resistor sizing). an averaging rms power detector compares the input signal amplitude with this threshold and feeds the signal-detect information to the open-col- lector los output. to prevent los chatter in the region of the pro- grammed threshold, approximately 2db of hysteresis is built into the los assert/deassert function. once asserted, the los is not deasserted until the input amplitude rises to the required level (v deassert ). (see figures 2 and 5.) design procedure program the los assert threshold external resistor, r th, programs the loss-of-signal threshold. see the los threshold vs. r th graph in the typical operating characteristics to select the appro- priate resistor. low-power, 622mbps to 3.2gbps limiting amplifier 8 _______________________________________________________________________________________ v cc i cc (supply current) i out (cml output current) 50 ? r th 50 ? MAX3746 figure 1. power-supply current measurement 1db 6db 0v signal on max deassert level min assert level power-detect window v in time signal off figure 2. los assert threshold set 1db below the minimum by receiver sensitivity for selected r th 50 ? 50 ? in+ in- 0.25pf 0.25pf v cc esd structures figure 3. cml input buffer q3 q4 q1 v cc 50 ? 50 ? q2 i2 = f (outpol, disable) i1 = f (outpol, disable) disable data out+ out- esd structures figure 4. cml output buffer
select the coupling capacitor when ac coupling is desired, coupling capacitors c in and c out should be selected to minimize the receiv- er? deterministic jitter. jitter is decreased as the input low-frequency cutoff (f in ) is decreased. f in = 1 / [2 (50)(c in )] for atm/sonet or other applications using scrambled nrz data, select (c in , c out ) 0.1?, which provides f in < 32khz. for fibre channel, gigabit ethernet, or other applications using 8b/10b data coding, select (c in , c out ) 0.01?, which provides f in < 320khz. refer to application note hfan-1.1, choosing ac- coupling capacitors . rssi implementation the sff-8472 digital diagnostic specification requires monitoring of input receive power. the MAX3746 and max3744 receiver chipset allows for the monitoring of the average receive power by measuring the average dc current of the photodiode. the max3744/max3724 preamp measures the aver- age photodiode current and provides the information to the output common mode. the MAX3746 rssi detect block senses the common-mode dc level of input sig- nals. in+ and in- provide a ground-referenced output signal (rssi) proportional to the photodiode current. the advantage of this implementation is that it allows the tia to be packaged in a low-cost, conventional 4- pin to-46 header. the MAX3746 rssi output is connected to an analog input channel of the ds1858/ds1859 sfp controller to convert the analog information into a 16-bit word. the ds1858/ds1859 provide the receive-power information to the host board of the optical receiver through a 2- wire interface. the ds1859 allows for internal calibra- tion of the receive power monitor. the max3744/max3724 and the MAX3746 have been optimized to achieve rssi stability of 2.5db within the 6? to 500? range of average input photodiode cur- rent. to achieve the best accuracy, maxim recom- mends receive-power calibration at the low end (6?) and the high end (500?) of the required range. see the rssi current gain graph in the typical operating characteristics . connecting to the dallas ds1858/ds1859 for best use of the rssi monitor, capacitor c1 and resistor r1 shown in the first typical application circuit need to be placed as close as possible to the dallas diagnostic monitor with the ground of c1 and r1 the same as the ds1858/ds1859 ground. capacitor c1 suppresses system noise on the rssi signal. r1 = 3k ? and c1 = 0.1? is recommended. emi performance the MAX3746 has been designed for better emi perfor- mance. to help reduce emi, special care has been taken to produce symmetrical signal outputs. see the eye diagram of the single-ended output in the typical operating characteristics . MAX3746 low-power, 622mbps to 3.2gbps limiting amplifier _______________________________________________________________________________________ 9 gnd esd structure v cc los figure 5. los output circuit outpol description v cc n oni nver ti ng outp ut w i th ful l c m l outp ut l evel open n oni nver ti ng outp ut w i th r ed uced c m l outp ut l evel 30k ? to gnd inverting output with reduced cml output level gnd inverting output with full cml output level table 1. logic table for polarity and cml output-level settings chip information transistor count: 1385 process: sige bipolar
MAX3746 low-power, 622mbps to 3.2gbps limiting amplifier 10 ______________________________________________________________________________________ 50 ? 50 ? out- out+ v cc 50 ? 50 ? v cc disable offset correction rssi detect power detect rssi in- in+ th los outpol MAX3746 outpol decode functional diagram t ypical operating circuits (continued) max3744 tia r1 3.01k ? c1 0.1 f in+ in- rssi th disable los outpol v cc gnd 4.7k ? to 10k ? los 2.97v to 3.6v out+ 50 ? 0.1 f out- 50 ? 0.1 f serdes supply filter host filter v cc_rx 5-pin to header host board sfp optical receiver pin or apd v cc (+3.3v or apd reference voltage) v cc (+3.3v) MAX3746 ds1859 3-input diagnostic monitor r th = 14k ?
MAX3746 low-power, 622mbps to 3.2gbps limiting amplifier ______________________________________________________________________________________ 11 t ypical operating circuits (continued) max3744 tia in+ in- rssi th disable los outpol v cc gnd 4.7k ? to 10k ? los 2.97v to 3.6v out+ 50 ? out- 50 ? c in 0.1 f c out 0.1 f c out 0.1 f c in 0.1 f serdes supply filter host filter v cc_rx 5-pin to header host board sfp optical receiver pin or apd v cc (+3.3v or apd reference voltage) v cc (+3.3v) max4004 MAX3746 ds1859 3-input diagnostic monitor r th = 14k ? 16 1 2 3 4 gnd v cc1 in+ in- v cc1 v cc2 out+ out- outpol 15 n.c. 14 n.c. 13 5 6 7 8 12 11 10 9 rssi th disable los gnd 3mm x 3mm qfn MAX3746 pin configuration
MAX3746 low-power, 622mbps to 3.2gbps limiting amplifier maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 12x16l qfn thin.eps 0.10 c 0.08 c 0.10 m c a b d d/2 e/2 e a1 a2 a e2 e2/2 l k e (nd - 1) x e (ne - 1) x e d2 d2/2 b l e l c l e c l l c l c e 1 2 21-0136 package outline 12, 16l, thin qfn, 3x3x0.8mm 1. dimensioning & tolerancing conform to asme y14.5m-1994. exposed pad variations 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220 revision c. notes: e 2 2 21-0136 package outline 12, 16l, thin qfn, 3x3x0.8mm down bonds allowed

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